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CY62146E MoBL(R)
4-Mbit (256K x 16) Static RAM
Features
* Very high speed: 45 ns * Wide voltage range: 4.5V-5.5V * Ultra low standby power -- Typical standby current: 1 A -- Maximum standby current: 7 A * Ultra low active power * * * * -- Typical active current: 2 mA @ f = 1 MHz Easy memory expansion with CE and OE features Automatic power down when deselected CMOS for optimum speed and power Offered in Pb-free 44-pin TSOP II package device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when: * Deselected (CE HIGH) * Outputs are disabled (OE HIGH) * Both byte high enable and byte low enable are disabled (BHE, BLE HIGH) * When the write operation is active (CE LOW and WE LOW) To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A17). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the "Truth Table" on page 9 for a complete description of read and write modes.
Functional Description[1]
The CY62146E is a high performance CMOS static RAM organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power down feature that reduces power consumption when addresses are not toggling. Placing the
Logic Block Diagram
DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
256K x 16 RAM Array
SENSE AMPS
IO0-IO7 IO8-IO15
COLUMN DECODER
BHE WE CE OE BLE
A11
A12
A13
A15
A14
Note 1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation Document #: 001-07970 Rev. *C
*
198 Champion Court
A16
A17
*
San Jose, CA 95134-1709
* 408-943-2600 Revised May 4, 2007
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CY62146E MoBL(R)
Pin Configurations
The figure that follows shows the 44-Pin TSOP II pinout.[2] Top View
A4 A3 A2 A1 A0 CE IO0 IO1 IO2 IO3 VCC VSS IO4 IO5 IO6 IO7 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE IO15 IO14 IO13 IO12 VSS VCC IO11 IO10 IO9 IO8 NC A8 A9 A10 A11 A12
Product Portfolio
Power Dissipation Product Range VCC Range (V) Min CY62146ELL Ind'l/Auto-A 4.5 Typ[3] 5.0 Max 5.5 45 ns Speed (ns) Typ[3] 2 Operating ICC (mA) f = 1 MHz Max 2.5 f = fmax Typ[3] 15 Max 20 Standby ISB2 (A) Typ[3] 1 Max 7
Notes 2. NC pins are not connected on the die. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25.
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Maximum Ratings
Exceeding maximum ratings may shorten the battery life of the device. User guidelines are not tested. Storage Temperature ................................ -65C to + 150C Ambient Temperature with Power Applied ........................................... -55C to + 125C Supply Voltage to Ground Potential ............................... -0.5V to + 6V (VCCmax + 0.5V) DC Voltage Applied to Outputs in High-Z State[4, 5] ....................-0.5V to 6V (VCCmax + 0.5V) DC Input Voltage[4, 5] ............... -0.5V to 6V (VCC max + 0.5V) Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage .......................................... >2001V (MIL-STD-883, Method 3015) Latch up Current...................................................... >200 mA
Operating Range
Device CY62146ELL Range Ind'l/Auto-A Ambient Temperature VCC[6]
-40C to +85C 4.5V to 5.5V
Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB2[7] Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Test Conditions IOH = -1.0 mA IOL = 2.1 mA VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V GND < VI < VCC GND < VO < VCC, Output Disabled 2.2 -0.5 -1 -1 15 2 1 45 ns (Ind'l/Auto-A) Min 2.4 0.4 VCC + 0.3 0.8 +1 +1 20 2.5 7 A Typ [3] Max Unit V V V V A A mA
VCC Operating Supply Current f = fmax = 1/tRC VCC = VCC(max) IOUT = 0 mA f = 1 MHz CMOS levels Automatic CE Power Down Current - CMOS Inputs CE > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = VCC(max)
Capacitance
For all packages. Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters. Parameter JA JC Description Thermal Resistance (junction to ambient) Thermal Resistance (junction to case) Test Conditions Still air, soldered on a 3 x 4.5 inch, two-layer printed circuit board TSOP II Package 77 13 Unit C/W C/W
Notes 4. VIL(min) = -2.0V for pulse durations less than 20 ns for I < 30 mA. 5. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 6. Full device AC operations are based on a minimum of 100 s ramp time from 0 to Vcc(min) and 200 s wait time after Vcc stabilization. 7. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
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AC Test Loads and Waveforms
Figure 1. AC Test Load and Waveforms VCC OUTPUT R1 3V 30 pF INCLUDING JIG AND SCOPE R2 10% GND RISE TIME= 1 V/ns ALL INPUT PULSES 90% 90% 10% FALL TIME= 1 V/ns
EQUIVALENT TO: THEVENIN EQUIVALENT RTH OUTPUT V 5.0V 1800 990 639 1.77 Unit V
Parameters R1 R2 RTH VTH
Data Retention Characteristics
Over the Operating Range Parameter VDR ICCDR [7] tCDR [8] tR [9] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = 2V, CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V Ind'l/Auto-A 0 tRC Conditions Min 2 1 7 Typ [3] Max Unit V A ns ns
Data Retention Waveform[10]
Figure 2. Data Retention Waveform
DATA RETENTION MODE VCC CE or BHE.BLE
VCC(min)
tCDR
VDR > 2.0V
VCC(min)
tR
Notes 8. Tested initially and after any design or process changes that may affect these parameters. 9. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 10. BHE. BLE is the AND of BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling BHE and BLE.
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Switching Characteristics
Over the Operating Range [11, 12] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Cycle[15] Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Setup to Write End Data Hold from Write End WE LOW to High-Z[13, 14]
[13]
Description
45 ns (Ind'l/Auto-A) Min 45 45 10 45 22 5 18 10 18 0 45 22 5 18 45 35 35 0 0 35 35 25 0 18 10 Max
Unit
Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to OE HIGH to CE LOW to CE HIGH to Low-Z[13] High-Z[13, 14] Low-Z[13] High-Z[13, 14]
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CE LOW to Power Up CE HIGH to Power Down BLE/BHE LOW to Data Valid BLE/BHE LOW to BLE/BHE HIGH to Low[13] High-Z[13, 14]
WE HIGH to Low-Z
Notes 11. Test conditions for all parameters other than tri-state parameters are based on signal transition time of 3 ns (1V/ns) or less, timing reference levels of 1.5V, input pulse levels of 0 to 3V, and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" on page 4. 12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 13. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output enters a high impedence state. 15. The internal memory write time is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
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Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[16, 17] Figure 3. Read Cycle No. 1 tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2 (OE Controlled)[17, 18] Figure 4. Read Cycle No. 2
ADDRESS
tRC CE tACE OE tDOE BHE/BLE tLZOE tHZBE tDBE tLZBE DATA OUT HIGHIMPEDANCE tLZCE tPU VCC SUPPLY CURRENT 50% 50% ICC ISB DATA VALID HIGH IMPEDANCE tHZOE tPD tHZCE
Notes 16. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL. 17. WE is HIGH for read cycle. 18. Address valid before or similar to CE and BHE, BLE transition LOW.
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Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[15, 19, 20] Figure 5. Write Cycle No. 1
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA
BHE/BLE
tBW
OE DATA IO NOTE 21 tHZOE
tSD DATAIN
tHD
Write Cycle No. 2 (CE Controlled)[15, 19, 20] Figure 6. Write Cycle No. 2
tWC ADDRESS tSCE CE
tSA
WE
tAW tPWE
tHA
BHE/BLE
tBW
OE tSD DATA IO NOTE 21 tHZOE
Notes 19. Data IO is high impedance if OE = VIH. 20. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 21. During this period, the IOs are in output state. Do not apply input signals.
tHD
DATAIN
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Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[20] Figure 7. Write Cycle No. 3
tWC ADDRESS tSCE CE
BHE/BLE tAW WE tSA
tBW tHA tPWE
tSD DATA IO NOTE 21 tHZWE DATAIN
tHD
tLZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[20] Figure 8. Write Cycle No. 4
tWC ADDRESS
CE tSCE
tAW BHE/BLE tSA WE
tHZWE
tHA tBW
tPWE tSD DATAIN
tLZWE
tHD
DATA IO
NOTE 21
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CY62146E MoBL(R)
Truth Table
CE H L L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE X H L H L L H L L H L BLE X H L L H L L H L L H Inputs Outputs High-Z High-Z Data Out (IO0-IO15) Data Out (IO0-IO7); IO8-IO15 in High-Z Data Out (IO8-IO15); IO0-IO7 in High-Z High-Z High-Z High-Z Data In (IO0-IO15) Data In (IO0-IO7); IO8-IO15 in High-Z Data In (IO8-IO15); IO0-IO7 in High-Z Mode Power Deselect/Power Down Standby (ISB) Output Disabled Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 45 45 Ordering Code CY62146ELL-45ZSXI CY62146ELL-45ZSXA Package Diagram Package Type Operating Range Industrial Automotive-A
51-85087 44-pin Thin Small Outline Package II (Pb-free) 51-85087 44-pin Thin Small Outline Package II (Pb-free)
Contact your local Cypress sales representative for availability of these parts.
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CY62146E MoBL(R)
Package Diagram
Figure 9. 44-Pin TSOP II, 51-85087
DIMENSION IN MM (INCH) MAX MIN.
22 1
PIN 1 I.D.
11.938 (0.470) 11.735 (0.462)
10.262 (0.404) 10.058 (0.396)
OR E KXA SG
23
44
EJECTOR PIN
TOP VIEW
BOTTOM VIEW
0.800 BSC (0.0315)
0.400(0.016) 0.300 (0.012)
BASE PLANE 0-5 0.10 (.004)
10.262 (0.404) 10.058 (0.396) 0.210 (0.0083) 0.120 (0.0047)
18.517 (0.729) 18.313 (0.721) 0.150 (0.0059) 0.050 (0.0020) 1.194 (0.047) 0.991 (0.039) SEATING PLANE
0.597 (0.0235) 0.406 (0.0160)
51-85087-*A
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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Document History Page
Document Title: CY62146E MoBL(R), 4-Mbit (256K x 16) Static RAM Document Number: 001-07970 REV. ** *A *B *C ECN NO. Issue Date 463213 684343 925501 1045260 See ECN See ECN See ECN See ECN Orig. of Change NXR VKN VKN VKN New Data Sheet Added Preliminary Automotive-A Information Updated Ordering Information Table Added footnote #8 related to ISB2 and ICCDR Added footnote #13 related AC timing parameters Converted Automotive-A specs from preliminary to final Description of Change
Document #: 001-07970 Rev. *C
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